Apparatus and methods for power amplifier biasing

ABSTRACT

Apparatus and methods for power amplifier biasing are disclosed herein. In certain implementations, a power amplifier system includes a power amplifier bias circuit and a power amplifier. The power amplifier bias circuit includes a reference current source that generates a reference current, a bipolar reference transistor, and a transimpedance amplifier that amplifies a difference between a collector current of the bipolar reference transistor and the reference current, and that provides a base bias voltage to a base of the bipolar reference transistor. The power amplifier generates a radio frequency output signal at an output based on amplifying a radio frequency input signal received at an input. The power amplifier includes a bipolar power amplifier transistor including a base biased by the base bias voltage such that the power amplifier has a substantially flat gain response versus time.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/428,932, filed Feb. 9, 2017 and titled “APPARATUS AND METHODS FORPOWER AMPLIFIER BIASING,” which is a continuation of U.S. patentapplication Ser. No. 15/144,515, filed May 2, 2016 and titled “APPARATUSAND METHODS FOR POWER AMPLIFIER BIAS CIRCUITS,” which is a continuationof U.S. patent application Ser. No. 14/448,793, filed Jul. 31, 2014 andtitled “APPARATUS AND METHODS FOR BIASING POWER AMPLIFIERS,” whichclaims the benefit of priority under 35 U.S.C. § 119(e) of U.S.Provisional Patent Application No. 61/861,309, filed Aug. 1, 2013entitled “APPARATUS AND METHODS FOR BIASING POWER AMPLIFIERS”, each ofwhich is herein incorporated by reference in its entirety.

BACKGROUND Field

Embodiments of the invention relate to electronic systems, and inparticular, to radio frequency (RF) electronics.

Description of the Related Technology

RF power amplifiers can be used to boost the power of an RF signalhaving a relatively low power. Thereafter, the boosted RF signal can beused for a variety of purposes, included driving the antenna of atransmitter.

Power amplifiers can be included in mobile phones to amplify an RFsignal for transmission. For example, in mobile phones that communicateusing a cellular standard, a wireless local area network (WLAN)standard, and/or any other suitable communication standard, a poweramplifier can be used to amplify the RF signal. It can be important tomanage the amplification of an RF signal, as amplifying the RF signal toan incorrect power level or introducing significant distortion of theoriginal RF signal can cause a wireless device to transmit out of bandor violate compliance with accepted standards. Biasing of a poweramplifier device is an important part of managing the amplificationbecause it can determine the voltage and/or current operating point ofthe amplifying devices within the power amplifier.

There is a need for improved power amplifier systems. Furthermore, thereis a need for improving power amplifier biasing.

SUMMARY

In certain embodiments, the present disclosure relates to a poweramplifier system. The power amplifier system includes a power amplifierconfigured to receive a radio frequency (RF) input signal, and toamplify the RF input signal to generate an RF output signal. The poweramplifier is further configured to receive a bias voltage that biasesthe power amplifier. The power amplifier system further includes a biascircuit configured to generate the bias voltage. The bias circuitincludes a bias circuit amplifier, a current source configured togenerate a reference current, and a reference transistor having acurrent therethrough that changes in relation to the bias voltage. Thebias circuit amplifier is configured to control the bias voltage basedon an error current corresponding to a difference between the referencecurrent and the current through the reference transistor.

In some embodiments, the bias circuit amplifier includes atransimpedance amplifier.

In various embodiments, the bias circuit is configured to receive anenable signal, and the bias circuit is configured to selectively turn onor off the power amplifier based on a state of the enable signal. In anumber of embodiments, at least one of the bias circuit amplifier or thecurrent source turns on or off based on the state of the enable signal.

According to certain embodiments, the power amplifier includes a bipolarpower amplifier transistor including a base that receives the biasvoltage. In some embodiments, the power amplifier system furtherincludes an array of transistor elements, and the bipolar poweramplifier transistor is implemented by a plurality of transistorelements of the array, and the reference transistor is implemented byone or more transistor elements of the array. According to variousembodiments, the bipolar power amplifier transistor and the referencetransistor are separated by a distance of less than about 9μm to providethermal coupling. In accordance with a number of embodiments, the poweramplifier system further includes an isolation circuit electricallyconnected between the base of the bipolar power amplifier transistor andan output of the bias circuit amplifier.

In several embodiments, the power amplifier includes a plurality ofpower amplifier stages arranged in a cascade.

According to some embodiments, the current source is a variable currentsource. In various embodiments, the power amplifier system furtherincludes a control circuit configured to control the reference currentgenerated by the variable current source to compensate for temperaturevariation.

In certain embodiments, the present disclosure relates to a method ofbiasing a power amplifier. The method includes generating a referencecurrent using a current source, controlling a current through areference transistor based on a bias voltage, generating an errorcurrent based on a difference between the reference current and thecurrent through the reference transistor, controlling a voltage level ofthe bias voltage based on amplifying the error current using a biascircuit amplifier, and biasing a power amplifier using the bias voltage.

In various embodiments, controlling the voltage level of the biasvoltage includes generating the bias voltage by amplifying the errorcurrent using a transimpedance amplifier.

According to some embodiments, controlling the voltage level of the biasvoltage includes using negative feedback to control the current throughthe reference transistor to substantially equal the reference current.

In several embodiments, the method includes pulsing an output of thepower amplifier by selectively activating at least one of the currentsource or the bias circuit amplifier using an enable signal.

In certain embodiments, the present disclosure relates to a poweramplifier bias circuit for biasing a power amplifier. The poweramplifier bias circuit includes a bias circuit amplifier, a currentsource configured to generate a reference current, and a referencetransistor having a current therethrough that changes in relation to abias voltage. The bias circuit amplifier is configured to control thebias voltage based on an error current corresponding to a differencebetween the reference current and the current through the referencetransistor.

According to some embodiments, the bias circuit amplifier includes atransimpedance amplifier.

In various embodiments, the current source is a variable current source.In some embodiments, the bias circuit amplifier further includes acontrol circuit configured to control the reference current generated bythe variable current source to compensate for temperature variation.

In several embodiments, at least one of the bias circuit amplifier orthe current source are turned on or off using an enable signal.

In certain embodiments, the present disclosure relates to a poweramplifier system. The power amplifier system includes a bipolar poweramplifier transistor having a base configured to receive an RF signaland a collector configured to generate an amplified RF signal. The baseof the bipolar power amplifier transistor is further configured toreceive a bias voltage. The power amplifier system further includes abias circuit configured to generate the bias voltage. The bias circuitincludes a bias circuit amplifier, a current source configured togenerate a reference current, and a bipolar reference transistor havinga base configured to receive the bias voltage and a collector configuredto generate a collector current. The bias circuit amplifier isconfigured to control the bias voltage based on a difference between thereference current and the collector current.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a power amplifier module for amplifyinga radio frequency (RF) signal.

FIG. 2 is a schematic block diagram of an example wireless device thatcan include one or more of the power amplifier modules of FIG. 1.

FIG. 3 is a schematic block diagram of one example of a power amplifiersystem.

FIG. 4 is a graph of one example of power amplifier gain versus time.

FIGS. 5A-5B are graphs of two examples of power amplifier gain versustime.

FIG. 6 is a schematic block diagram of another example of a poweramplifier system.

FIG. 7 is a circuit diagram of one embodiment of a power amplifiersystem.

FIG. 8 is a circuit diagram of another embodiment of a power amplifiersystem.

FIG. 9A is a circuit diagram of a multi-stage power amplifier accordingto one embodiment.

FIG. 9B is a circuit diagram of a multi-stage power amplifier accordingto another embodiment.

FIG. 10A is a schematic diagram of one embodiment of a packaged poweramplifier module.

FIG. 10B is a schematic diagram of a cross-section of the packaged poweramplifier module of FIG. 10A taken along the lines 10B-10B.

DETAILED DESCRIPTION OF EMBODIMENTS

The headings provided herein, if any, are for convenience only and donot necessarily affect the scope or meaning of the claimed invention.

Apparatus and methods for biasing power amplifiers are disclosed herein.In certain implementations, a power amplifier system including a poweramplifier and a bias circuit is provided. The power amplifier can beused to amplify a radio frequency (RF) signal for transmission, and thebias circuit can be used to generate a bias voltage for biasing thepower amplifier. The power amplifier bias circuit can receive an enablesignal that can be used to enable or disable the power amplifier so asto pulse the power amplifier's output.

In certain implementations, the bias circuit includes an amplifier, acurrent source for generating a reference current, and a referencetransistor having a current therethrough that changes in relation to thebias voltage. The amplifier can control the bias voltage based on anerror current corresponding to a difference between the referencecurrent and the current through the reference transistor. For example,the amplifier can be used to control the bias voltage such that thereference current and the current through the reference transistor aresubstantially equal.

By configuring the bias circuit in this manner, the bias circuit cangenerate a bias voltage that changes dynamically over time to controlthe current through the reference transistor to be substantially equalto the reference current. The power amplifier can be biased based on thebias voltage such that the power amplifier has a substantially flat gainresponse versus time. Correcting for gain variation in the poweramplifier can improve the power amplifier's performance, including, forexample, the power amplifier's dynamic error vector magnitude (DEVM). Incertain configurations, the bias circuit can also be used to compensatefor variation in other power amplifier parameters, including, forexample, variation in the power amplifier's phase across temperature.

Overview of Examples of Power Amplifier Systems

FIG. 1 is a schematic diagram of a power amplifier module 10 foramplifying a radio frequency (RF) signal. The illustrated poweramplifier module (PAM) 10 can be configured to amplify an RF signalRF_IN to generate an amplified RF signal RF_OUT. As described herein,the power amplifier module 10 can include one or more power amplifiers,including, for example, multi-stage power amplifiers.

FIG. 2 is a schematic block diagram of an example wireless or mobiledevice 11 that can include one or more of the power amplifier modules ofFIG. 1. The wireless device 11 can include power amplifier bias circuitsimplementing one or more features of the present disclosure.

The example wireless device 11 depicted in FIG. 2 can represent amulti-band and/or multi-mode device such as a multi-band/multi-modemobile phone. In the illustrated configuration, the wireless device 11includes switches 12, a transceiver 13, an antenna 14, power amplifiers17, a control component 18, a computer readable medium 19, a processor20, and a battery 21.

The transceiver 13 can generate RF signals for transmission via theantenna 14. Furthermore, the transceiver 13 can receive incoming RFsignals from the antenna 14.

It will be understood that various functionalities associated with thetransmission and receiving of RF signals can be achieved by one or morecomponents that are collectively represented in FIG. 2 as thetransceiver 13. For example, a single component can be configured toprovide both transmitting and receiving functionalities. In anotherexample, transmitting and receiving functionalities can be provided byseparate components.

Similarly, it will be understood that various antenna functionalitiesassociated with the transmission and receiving of RF signals can beachieved by one or more components that are collectively represented inFIG. 2 as the antenna 14. For example, a single antenna can beconfigured to provide both transmitting and receiving functionalities.In another example, transmitting and receiving functionalities can beprovided by separate antennas. In yet another example, different bandsassociated with the wireless device 11 can be provided with differentantennas.

In FIG. 2, one or more output signals from the transceiver 13 aredepicted as being provided to the antenna 14 via one or moretransmission paths 15. In the example shown, different transmissionpaths 15 can represent output paths associated with different bandsand/or different power outputs. For instance, the two example poweramplifiers 17 shown can represent amplifications associated withdifferent power output configurations (e.g., low power output and highpower output), and/or amplifications associated with different bands.Although FIG. 2 illustrates a configuration using two transmission paths15, the wireless device 11 can be adapted to include more or fewertransmission paths 15.

The power amplifiers 17 can be used to amplify a wide variety of RFsignals. For example, one or more of the power amplifiers 17 can receivean enable signal that can be used to pulse the output of the poweramplifier to aid in transmitting a wireless local area network (WLAN)signal or any other suitable pulsed signal. In certain configurations,one or more of the power amplifiers 17 are configured to amplify a Wi-Fisignal. Each of the power amplifiers 17 need not amplify the same typeof signal. For example, one power amplifier can amplify a WLAN signal,while another power amplifier can amplify, for example, a Global Systemfor Mobile (GSM) signal, a code division multiple access (CDMA) signal,a W-CDMA signal, a Long Term Evolution (LTE) signal, or an EDGE signal.

One or more features of the present disclosure can be implemented in theforegoing example modes and/or bands, and in other communicationstandards.

In FIG. 2, one or more detected signals from the antenna 14 are depictedas being provided to the transceiver 13 via one or more receiving paths16. In the example shown, different receiving paths 16 can representpaths associated with different bands. Although FIG. 2 illustrates aconfiguration using four receiving paths 16, the wireless device 11 canbe adapted to include more or fewer receiving paths 16.

To facilitate switching between receive and transmit paths, the switches12 can be configured to electrically connect the antenna 14 to aselected transmit or receive path. Thus, the switches 12 can provide anumber of switching functionalities associated with an operation of thewireless device 11. In certain configurations, the switches 12 caninclude a number of switches that provide functionalities associatedwith, for example, switching between different bands, switching betweendifferent power modes, switching between transmission and receivingmodes, or some combination thereof. The switches 12 can also provideadditional functionality, including filtering and/or duplexing ofsignals.

FIG. 2 shows that in certain configurations, a control component 18 canbe provided for controlling various control functionalities associatedwith operations of the switches 12, the power amplifiers 17, and/orother operating component(s), such as bias circuits. Non-limitingexamples of the control component 18 are described herein in greaterdetail.

In certain configurations, a processor 20 can be configured tofacilitate implementation of various processes described herein. Theprocessor 20 can operate using computer program instructions. Thesecomputer program instructions may be provided to the processor 20.

In certain configurations, these computer program instructions may alsobe stored in a computer-readable memory 19 that can direct the processor20 or other programmable data processing apparatus to operate in aparticular manner.

The battery 21 can be any suitable battery for use in the wirelessdevice 11, including, for example, a lithium-ion battery.

FIG. 3 is a schematic block diagram of one example of a power amplifiersystem 26. The illustrated power amplifier system 26 includes theswitches 12, the antenna 14, the battery 21, a directional coupler 24, apower amplifier bias circuit 30, a power amplifier 32, and a transceiver33. The illustrated transceiver 33 includes a baseband processor 34, anI/Q modulator 37, a mixer 38, and an analog-to-digital converter (ADC)39. Although not illustrated in FIG. 3 for clarity, the transceiver 33can include circuitry associated with receiving signals over one or morereceive paths.

The baseband signal processor 34 can be used to generate an I signal anda Q signal, which can be used to represent a sinusoidal wave or signalof a desired amplitude, frequency, and phase. For example, the I signalcan be used to represent an in-phase component of the sinusoidal waveand the Q signal can be used to represent a quadrature component of thesinusoidal wave, which can be an equivalent representation of thesinusoidal wave. In certain implementations, the I and Q signals can beprovided to the I/Q modulator 37 in a digital format. The basebandprocessor 34 can be any suitable processor configured to process abaseband signal. For instance, the baseband processor 34 can include adigital signal processor, a microprocessor, a programmable core, or anycombination thereof. Moreover, in some implementations, two or morebaseband processors 34 can be included in the power amplifier system 26.

The I/Q modulator 37 can be configured to receive the I and Q signalsfrom the baseband processor 34 and to process the I and Q signals togenerate an RF signal. For example, the I/Q modulator 37 can includeDACs configured to convert the I and Q signals into an analog format,mixers for upconverting the I and Q signals to radio frequency, and asignal combiner for combining the upconverted I and Q signals into an RFsignal suitable for amplification by the power amplifier 32. In certainimplementations, the I/Q modulator 37 can include one or more filtersconfigured to filter frequency content of signals processed therein.

The power amplifier bias circuit 30 can receive an enable signal ENABLEfrom the baseband processor 34 and a battery or power high voltageV_(CC) from the battery 21, and can use the enable signal ENABLE togenerate a bias voltage V_(BIAS) for the power amplifier 32.

Although FIG. 3 illustrates the battery 21 directly generating the powerhigh voltage V_(CC), in certain implementations the power high voltageV_(CC) can be a regulated voltage generated by a regulator that ispowered using the battery 21. In one example, a switching regulator,such as a buck and/or boost converter, can be used to generate the powerhigh voltage V_(CC).

The power amplifier 32 can receive the RF signal from the I/Q modulator37 of the transceiver 33, and can provide an amplified RF signal to theantenna 14 through the switches 12.

The directional coupler 24 can be positioned between the output of thepower amplifier 32 and the input of the switches 12, thereby allowing anoutput power measurement of the power amplifier 32 that does not includeinsertion loss of the switches 12. The sensed output signal from thedirectional coupler 24 can be provided to the mixer 38, which canmultiply the sensed output signal by a reference signal of a controlledfrequency so as to downshift the frequency content of the sensed outputsignal to generate a downshifted signal. The downshifted signal can beprovided to the ADC 39, which can convert the downshifted signal to adigital format suitable for processing by the baseband processor 34.

By including a feedback path between the output of the power amplifier32 and the baseband processor 34, the baseband processor 34 can beconfigured to dynamically adjust the I and Q signals to optimize theoperation of the power amplifier system 26. For example, configuring thepower amplifier system 26 in this manner can aid in controlling thepower added efficiency (PAE) and/or linearity of the power amplifier 32.

FIG. 4 is a graph 40 of one example of power amplifier gain versus time.The graph 40 includes an initial phase Φ₀, in which the power amplifieris disabled and has a relatively low gain, such as a gain of about 0. Atthe end of the initial phase Φ₀, the power amplifier is enabled. Forexample, the initial phase Φ₀ can end in response to transitioning theenable signal ENABLE shown in FIG. 3 from a deactivated state to anactivated state.

As shown in FIG. 4, after being enabled, the power amplifier can have atime-dependent gain associated with the power amplifier operating indifferent phases associated with different gain amounts. For example,the power amplifier can include a first phase Φ₁, in which the poweramplifier's gain can begin to settle based on a dominant influencingfactor. Additionally, the power amplifier can include a second phase Φ₂in which gain can further settle based on one or more non-dominantinfluencing factors. Furthermore, in a third phase Φ₃, the poweramplifier's gain can be settled and substantially constant. In the thirdphase Φ₃, the power amplifier amplifier's error vector magnitude (EVM)can correspond to the power amplifier's static error vector magnitude(SEVM).

A power amplifier's gain can settle over time for a variety of reasons.For example, physical circuit limitations may prevent an amplifier fromturning on instantaneously. Additionally, when the power amplifier isactivated, the power amplifier may begin to heat, which can lead to athermal transient that changes the performance characteristics of thepower amplifier's circuitry. The thermal transient can be affected by avariety of factors, including self-heating of devices, mutual heating ofdevices, thermal mismatch between devices, and/or cross-die heattransfer.

In certain applications, a power amplifier can provide amplificationbefore the gain of the power amplifier is fully settled. For example,the power amplifier may provide amplification during the second phaseΦ₂, since the power amplifier's thermal time constant may be much longerthan the amplifier's rated or specified turn-on time. Before the poweramplifier's gain is settled, the power amplifier can have a dynamicerror vector magnitude (DEVM) that can be worse that the poweramplifier's SEVM.

From a system perspective, the distortion associated with amplifying anRF input signal using a power amplifier can be represented by either theDEVM or SEVM figure of merit (FOM).

It can be undesirable for a power amplifier to have a time-dependentgain after turn on. For example, when a power amplifier has atime-dependent gain, the distortion that the RF input signal undergoesduring amplification can be different shortly after the power amplifieris activated relative to when the power amplifier has reached asteady-state gain condition. Since a receiver demodulation level can beset during a preamble, any change in gain after the receiverdemodulation level is set can cause error and poor EVM.

Although FIG. 4 illustrates the power amplifier's gain changing acrosstime, persons having ordinary skill in the art will appreciate thatother parameters of the power amplifier can change with time, including,for example, the power amplifier's phase. The teachings herein areapplicable not only to provide gain correction, but also to provideother types of correction, such as phase correction.

FIGS. 5A-5B are graphs of two examples of power amplifier gain versustime. FIG. 5A includes a first graph 41 of power amplifier gain versustime, and FIG. 5B includes a second graph 42 of power amplifier gainversus time.

The first graph 41 of FIG. 5A illustrates a configuration in which apower amplifier is turned off for a relatively long duration betweenactivation events or pulses. For example, the first graph 41 includes afirst activation event 43 a and a second activation event 43 b that areseparated by a relatively long delay. In contrast, the second graph 42of FIG. 5B illustrates a configuration in which a power amplifier isturned off for a relatively brief duration between activation events.For example, the second graph 42 includes a first activation event 44 aand a second activation event 44 that are separately by a relativelyshort delay.

In the configuration shown in FIG. 5A, the temperature of the poweramplifier can be relatively cold at the start of the second activationevent 43 b, since the duration of time between the first and secondactivation events 43 a, 43 b is relatively long. The relatively coldtemperature of the power amplifier can increase the impact of transientgain effects associated with pulsing operations of the power amplifier.In contrast, in the configuration shown in FIG. 5B, the temperature ofthe power amplifier can be relatively hot at the start of the secondactivation event 44 b, which can result in the power amplifier having arelatively small amount of transient gain effects.

Absent compensation, the DEVM of the power amplifier can vary based onthe pulsing operations of the power amplifier, including, for example,an off-time between pulses and/or a duty cycle of the pulses. The timedependence of the power amplifier's gain and/or phase on pulsingoperations can make it difficult to compensate for the power amplifier'sDEVM using static techniques, such as resistor-capacitor (RC)compensation.

FIG. 6 is a schematic block diagram of another example of a poweramplifier system 60. The illustrated power amplifier system 60 includesa power amplifier bias circuit 51, the battery 21, the power amplifier32, an inductor 62, a decoupling capacitor 63, a DC blocking capacitor52, an impedance matching block 64, the switches 12, and the antenna 14.

The illustrated power amplifier 32 includes a bipolar power amplifiertransistor 61 having an emitter, a base, and a collector. The emitter ofthe bipolar power amplifier transistor 61 can be electrically connectedto a first or power low voltage V₁, which can be, for example, a groundsupply. Additionally, a radio frequency (RF) input signal RF_IN can beprovided to the base of the bipolar power amplifier transistor 61through the DC blocking capacitor 52. The bipolar power amplifiertransistor 61 can amplify the RF input signal RF_IN and provide theamplified RF signal at the collector. The bipolar power amplifiertransistor 61 can be any suitable device. In one implementation, thebipolar power amplifier transistor 61 is a heterojunction bipolartransistor (HBT).

The power amplifier 32 can be configured to provide the amplified RFsignal to the switches 12. Although illustrated for a configurationusing a single stage, the power amplifier 32 can be adapted to includemultiple stages.

The battery 21 can be any suitable battery, such as a lithium-ionbattery, and be used to provide the power high voltage V_(CC) to thepower amplifier 32 and, in certain configurations, to the poweramplifier bias circuit 51. Although the power amplifier system 60illustrates the battery 21 as directly generating the power high voltageV_(CC), in certain configurations, the power amplifier system 60 caninclude a regulator that is used to generate the power high voltageV_(CC). Accordingly, the teachings herein are applicable toconfigurations in which a power amplifier is powered directed using abattery voltage and to configurations in which a power amplifier ispowered using a regulated voltage.

The impedance matching block 64 can be used to aid in terminating theelectrical connection between the output of the power amplifier 32 andan input of the switches 12. For example, the impedance matching block64 can be used to increase power transfer and/or reduce reflections ofthe amplified RF signal.

The inductor 62 can be included to aid in powering the power amplifier32 with the power high voltage V_(CC) while choking or blocking highfrequency RF signal components. The inductor 62 can include a first endelectrically connected to the power high voltage V_(CC) and a second endelectrically connected to the collector of the bipolar power amplifiertransistor 61. The decoupling capacitor 63 is electrically connectedbetween the power high voltage V_(CC) and the power low voltage V₁ andcan provide a low impedance path to high frequency signals, therebyreducing the noise of the power high voltage V_(CC), improving poweramplifier stability, and/or improving the performance of the inductor 62as an RF choke.

The power amplifier bias circuit 51 is configured to receive an enablesignal ENABLE and the power high voltage V_(CC). The power amplifierbias circuit 51 can use the enable signal ENABLE to generate a biasvoltage V_(BIAS) for biasing the power amplifier 32. For example, asillustrated in FIG. 6, the power amplifier bias circuit 51 can be usedto generate a bias voltage V_(BIAS) that can be used to bias the base ofthe bipolar power amplifier transistor 61 of the power amplifier 32.

The power amplifier bias circuit 51 can use the enable signal ENABLE tocontrol a magnitude of the bias voltage V_(BIAS) over time so as toenable or disable the power amplifier and thereby pulse the poweramplifier's output. For example, when the enable signal ENABLE indicatesthe power amplifier 32 should be activated, the power amplifier biascircuit 51 can change the amplitude of the bias voltage V_(BIAS) so asto achieve a desired gain of the power amplifier 32. Similarly, when theenable signal ENABLE indicates that the power amplifier 32 should bedeactivated, the power amplifier bias circuit 51 can decrease the biasvoltage V_(BIAS) such that the gain of the power amplifier 32 isrelative low, for example, about 0.

Although FIG. 6 illustrates one implementation of the power amplifier32, skilled artisans will appreciate that the teachings described hereincan be applied to a variety of power amplifier structures, including,for example, multi-stage power amplifier structures and/or poweramplifiers employing other transistor structures.

Overview of Power Amplifier Bias Circuits

FIG. 7 is a circuit diagram of a power amplifier system 70 according toone embodiment. The power amplifier system 70 includes the battery 21,the power amplifier 32, the DC blocking capacitor 52, the inductor 62,and the decoupling capacitor 63, which can be as described earlier. Thepower amplifier system 70 further includes a power amplifier biascircuit 55.

The power amplifier bias circuit 55 includes a current source 71, abipolar reference transistor 72, and a bias circuit amplifier oramplifier 73. The current source 71 is configured to generate areference current I_(REF), and the bipolar reference transistor 72 has acollector current I_(C). As shown in FIG. 7, the amplifier 73 includesan input configured to receive an error current I_(ERROR), which cancorrespond to a difference between the reference current I_(REF) and thecollector current I_(C). The amplifier 73 further includes an outputconfigured to generate a bias voltage V_(BIAS), which can be provided tothe base of the bipolar reference transistor 72 and to the base of thebipolar power amplifier transistor 61.

In certain configurations, the power amplifier bias circuit 55 and thepower amplifier 32 can be integrated on a single die with one or moreother components to form a packaged power amplifier module, which canbe, for example, mounted or attached to an RF circuit board associated awireless device, such as the wireless device 11 of FIG. 2.

As shown in FIG. 7, the amplifier 73 can be used to control a voltagelevel of the bias voltage V_(BIAS). Additionally, the amplifier 73 andthe bipolar reference transistor 72 are electrically connected in anegative feedback loop, and the amplifier 73 can control the voltagelevel of the bias voltage V_(BIAS) to control the error currentI_(ERROR) to be about equal to 0 mA, which can correspond to anoperating condition in which the collector current I_(C) is about equalto the reference current I_(REF).

In certain configurations, the amplifier 73 is a transimpedanceamplifier configured to amplify the error current I_(ERROR) to generatethe bias voltage V_(BIAS). However, other configurations are possible,including, for example, implementations in which the amplifier 73includes a current-to-voltage converter and an operational amplifierarranged in a cascade.

In the illustrated configuration, the bias circuit 55 is configured toreceive an enabled signal ENABLE, which can be used to selectively pulsethe output of the power amplifier 32 based on the enable signal's state.For example, when the power amplifier 32 is configured to transmit aWLAN signal, such as a Wi-Fi signal, the enable signal ENABLE can beselectively controlled so as to pulse the output of the power amplifier32. In certain configurations, the amplifier 73 and/or the currentsource 71 are selectively activated or turned on and off using theenable signal ENABLE. Configuring the bias circuit 55 in this manner canaid in controlling the voltage level of the bias voltage V_(BIAS) so asto pulse the power amplifier's output. Although the current source 71and the amplifier 73 both receive the enable signal ENABLE in theillustrated configuration, other implementations are possible.

Absent compensation, the gain and/or phase of the power amplifier 32 canchange over time. For example, the power amplifier's gain and/or phasecan change based on thermal effects and/or the level of the power highvoltage V_(CC), which can vary depending on a battery charge level ofthe wireless device that the power amplifier 32 and the power amplifierbias circuit 55 are used in. The power amplifier bias circuit 55 can beused to compensate for a gain and/or phase variation of the poweramplifier 32 arising from such sources, as well as from other sources.

For example, in certain implementations, the bipolar referencetransistor 72 can be configured to be a scaled replica of the bipolarpower amplifier transistor 61. Additionally, the feedback loopassociated with the amplifier 73 and the bipolar reference transistor 72can result in the amplifier 73 controlling the voltage level of the biasvoltage V_(BIAS) such that the collector current I_(C) of the bipolarreference transistor 72 is about equal to the reference current I_(REF).Since the bipolar reference transistor 72 can be a scaled replica of thebipolar power amplifier transistor 61 and can receive the bias voltageV_(BIAS), or a modified version thereof, a bias current of the bipolarpower amplifier transistor 61 can change in relation to the referencecurrent I_(REF).

For example, in certain configurations, the bias circuit 55 can be usedto control a bias current of the bipolar power amplifier transistor 61to be about equal to n*I_(REF), where n is a factor corresponding to ascaling ratio between the bipolar power amplifier transistor 61 and thebipolar reference transistor 72. In certain implementations, the bipolarreference transistor 72 can be a factor of n smaller than the bipolarpower amplifier transistor 61 to reduce static power dissipation of thebias circuit 55 relative to a configuration in which the bipolarreference transistor 72 and the bipolar power amplifier transistor 61have equal size.

Accordingly, the bias circuit 55 can be used to correct for a variationin gain and/or phase over time that can occur shortly after the poweramplifier 32 is enabled. For example, the bias circuit 55 can be used tocontrol the gain and/or phase of the power amplifier 32 to besubstantially constant even in the presence of time-dependent thermalchanges.

In certain implementations, the bipolar reference transistor 72 and thebipolar power amplifier transistor 61 can be thermally coupled andoperate under similar biasing conditions, and thus can have similartemperatures and power densities. By operating the bipolar referencetransistor 72 and the bipolar power amplifier transistor 61 with similartemperature and/or power densities, the bias circuit 55 can provideenhanced DEVM compensation. For example, the illustrated configurationcan provide enhanced performance relative to a scheme that generates thebias voltage using a current mirror, since such current mirrortransistors and the power amplifier transistor can operate withdifferent power densities.

FIG. 8 is a circuit diagram of a power amplifier system 80 according toanother embodiment. The power amplifier system 80 includes the DCblocking capacitor 52 and the bias circuit 55, which can be as describedearlier. The power amplifier system 80 further includes a power highbias circuit 81 and a power amplifier 82. The power high bias circuit 81can be used to provide a power high voltage to the power amplifier 82.

As described earlier, the bias circuit 55 includes the current source71, the bipolar reference transistor 72, and the amplifier 73. In theillustrated configuration, the bias circuit 55 has been used to generatea bias voltage V_(BIAS) for a power amplifier transistor, which has beenimplemented using transistor elements 61 a-61 d selected from atransistor array 83.

In certain implementations, a power amplifier transistor is implementedusing a plurality of transistor elements selected from a transistorarray, such as the transistor array 83 of FIG. 8. Implementing a poweramplifier transistor in this manner can aid in reducing parasiticeffects and/or otherwise enhancing the performance of the poweramplifier.

In certain configurations, the reference bipolar transistor 72 is alsoimplemented using one or more transistor elements selected from thetransistor array 83 used to implement the power amplifier transistor.The transistor elements of the transistor array 83 can be implemented ina common layout with substantially the same geometry and size relativeto one another. Implementing the bipolar reference transistor 72 in thismanner can improve transistor matching of the bipolar referencetransistor 72 and the power amplifier transistor associated withfabrication or processing.

Furthermore, implementing the reference transistor 72 in this manner canalso improve thermal coupling between the reference transistor 72 andthe power amplifier transistor, which can reduce the power amplifier'sgain and/or phase variation associated with thermal mismatch. In oneembodiment, to provide robust thermal coupling, the reference transistor72 and the power amplifier transistor are separated by less than about 9μm.

FIG. 9A is a circuit diagram of a multi-stage power amplifier 90according to one embodiment. The multi-stage power amplifier 90 includesa first variable current source 91 a, a second variable current source91 b, a third variable current source 91 c, a first power amplifierstage 95 a, a second power amplifier stage 95 b, a third power amplifierstage 95 c, a first feedback bias circuit 96 a, a second feedback biascircuit 96 b, a third feedback bias circuit 96 c, and a control circuit97.

As schematically illustrated using arrows, the first power amplifierstage 95 a, the second power amplifier stage 95 b, and the third poweramplifier stage 95 c are arranged in a cascade. For example, an input ofthe first power amplifier stage 95 a can receive an RF input signal, aninput of second power amplifier stage 95 b can be electrically connectedto the output of the first power amplifier stage 95 a, the input of thethird power amplifier stage 95 c can be electrically connected to theoutput of the second power amplifier stage 95 b, and an output of thethird power amplifier stage 95 c can generate an amplified RF signal.Although the multi-stage power amplifier 90 illustrates a configurationusing three power amplifier stages, the multi-stage power amplifier 90can include more or fewer power amplifier stages.

In the illustrated configuration, the first to third variable currentsources 91 a-91 c are controlled using a control circuit 97. The controlcircuit 97 can be used to control the first, second, and third variablecurrent sources 91 a, 91 b, 91 c such that the first, second, and thirdreference currents I_(REF1), I_(REF2), I_(REF3) generated by the currentsources have a relatively small variation across temperature. Forexample, in one embodiment, the control circuit 97 includes a bandgapreference circuit, which can be used to generate a reference signal thatis substantially independent of temperature and can be used to controlthe current sources. In certain configurations, the control circuit 97receives an enable signal that can be used to selectively pulse theoutput of the power amplifier.

As shown in FIG. 9A, the third power amplifier stage 95 c includes aplurality of transistor arrays which have been used to implement poweramplifier and reference transistors. For example, in the illustratedconfiguration, the third power amplifier stage 95 c includes first tofourth transistor arrays 94 a-94 d. In the illustrated configuration,the first to fourth reference transistors 92 a-92 d are implementedwithin the first to fourth transistors arrays 94 a-94 d, respectively.Additionally, at least a portion of the remaining transistor elements ofthe first to fourth transistor arrays 94 a-94 d can be electricallyconnected to one another to operate as a bipolar power amplifiertransistor associated with the third power amplifier stage 95 c.Electrical connections associated with the array of transistors 61 a-61d have been omitted for clarity of the figures.

In the configuration shown in FIG. 9A, each power amplifier stage 95a-95 c is biased in part using a feedback bias circuit. For example, thethird feedback bias circuit 96 c includes a transimpedance amplifier 93,which can be used to generate a bias voltage for the power amplifiertransistor of the third power amplifier stage 95 c. The transimpedanceamplifier 93 can generate a bias voltage for the third power amplifierstage 95 c based on amplifying an error current corresponding to adifference between the third reference current I_(REF3) and a collectorcurrent of the first reference transistor 92 a. Since the transimpedanceamplifier 93 operates with negative feedback, the transimpedanceamplifier 93 can control the collector current of the first referencetransistor 92 a to be substantially equal to the third reference currentI_(REF3) generated by the third variable current source 91 c.

In certain implementations, selection circuitry (not illustrated in FIG.9A) such as multiplexers can be used to selectively connect one of thefirst to fourth reference transistors 92 a-92 d to the third feedbackbias circuit 96 c. For example, as shown in FIG. 9A, the collector ofthe first reference transistor 92 a has been electrically connected toan input of the transimpedance amplifier 93, and the base of the firstreference transistor 92 a has been electrically connected to an outputof the transimpedance amplifier 93. By including a plurality ofreference transistors, a reference transistor that best tracks a thermaltemperature of the power amplifier stage can be used for generating thestage's bias voltage.

In another implementation, a bias voltage for a power amplifier stagecan be generated using multiple reference transistors. For example, twoor more of the reference transistors can be electrically connected inparallel and to the third feedback circuit 96 c such that the biasvoltage generated for the power amplifier stage is based on an averageof the reference transistors. The two or more of the referencetransistors can be selected using selection circuitry (not illustratedin FIG. 9A) or electrically connected in parallel using interconnect.

Although not illustrated in FIG. 9A for clarity, the first and secondpower amplifier stages 95 a, 95 b can include circuitry similar to thethird power amplifier stage 95 c. Additionally, the first and secondfeedback bias circuits 96 a, 96 b can include circuitry similar to thatof the third feedback bias circuit 96 c. Although FIG. 9A illustrates aconfiguration in which each power amplifier stage of the multi-stagepower amplifier is biased using a feedback bias circuit, the teachingsherein are applicable to configurations in which less than all of apower amplifier's stages use a feedback bias circuit. For example, incertain configurations, only an output stage of a power amplifier isbiased using a feedback bias circuit.

FIG. 9B is a circuit diagram of a multi-stage power amplifier 100according to another embodiment. The multi-stage power amplifier 100 ofFIG. 9B is similar to the multi-stage power amplifier 90 of FIG. 9A,except that the multi-stage power amplifier 100 further includes a firstisolation circuit 98 a, a second isolation circuit 98 b, and a thirdisolation circuit 98 c.

Additionally, the third power amplifier stage 95 c is illustrated asincluding a selection circuit 99, which can be used to selectivelyconnect one or more of the first reference transistor 92 a, the secondreference transistor 92 b, the third reference transistor 92 c, and/orthe fourth reference transistor 92 d to the third feedback bias circuit96 c. In configurations in which more than one reference transistor isselected, the selected reference transistors can be electricallyconnected in parallel with one another such that the bias voltagegenerated for the third power amplifier stage 100 is based on an averageof the selected reference transistors.

The first to third isolation circuits 98 a-98 c can be used to providebias voltages to the power amplifier transistors while helping toprevent noise from reaching the bias circuit. In one embodiment, thethird isolation circuit 98 c comprises at least one of an inductor or aresistor. Similarly, in certain configurations, the first and secondisolation circuits 98 a, 98 b can each comprise at least one of aninductor or a resistor. Although FIG. 9B illustrates a configuration inwhich an isolation circuit is included for each power amplifier stage,in other configurations, an isolation circuit is included for less thanall power amplifier stages.

FIG. 10A is a schematic diagram of one embodiment of a packaged poweramplifier module 300. FIG. 10B is a schematic diagram of a cross-sectionof the packaged power amplifier module 300 of FIG. 10A taken along thelines 10B-10B.

The packaged power amplifier module 300 includes an IC or die 301,surface mount components 303, wirebonds 308, a package substrate 320,and encapsulation structure 340. The package substrate 320 includes pads306 formed from conductors disposed therein. Additionally, the die 301includes pads 304, and the wirebonds 308 have been used to electricallyconnect the pads 304 of the die 301 to the pads 306 of the packagesubstrate 301.

As illustrated in FIGS. 10A and 10B, the die 301 includes the poweramplifier 32 and the power amplifier bias circuit 55 formed therein. Thepower amplifier bias circuit 55 includes the current source 71, thereference transistor 72, and the power amplifier 73, which can be asdescribed earlier.

The packaging substrate 320 can be configured to receive a plurality ofcomponents such as the die 301 and the surface mount components 303,which can include, for example, surface mount capacitors and/orinductors.

As shown in FIG. 10B, the packaged power amplifier module 300 is shownto include a plurality of contact pads 332 disposed on the side of thepackaged power amplifier module 300 opposite the side used to mount thedie 301. Configuring the packaged power amplifier module 300 in thismanner can aid in connecting the packaged power amplifier module 300 toa circuit board such as a phone board of a wireless device. The examplecontact pads 332 can be configured to provide RF signals, bias signals,power low voltage(s) and/or power high voltage(s) to the die 301 and/orthe surface mount components 303. As shown in FIG. 10B, the electricallyconnections between the contact pads 332 and the die 301 can befacilitated by connections 333 through the package substrate 320. Theconnections 333 can represent electrical paths formed through thepackage substrate 320, such as connections associated with vias andconductors of a multilayer laminated package substrate.

In some embodiments, the packaged power amplifier module 300 can alsoinclude one or more packaging structures to, for example, provideprotection and/or to facilitate handling of the packaged power amplifiermodule 300. Such a packaging structure can include overmold orencapsulation structure 340 formed over the packaging substrate 320 andthe components and die(s) disposed thereon.

It will be understood that although the packaged power amplifier module300 is described in the context of electrical connections based onwirebonds, one or more features of the present disclosure can also beimplemented in other packaging configurations, including, for example,flip-chip configurations.

APPLICATIONS

Some of the embodiments described above have provided examples inconnection with mobile phones. However, the principles and advantages ofthe embodiments can be used for any other systems or apparatus that haveneeds for power amplifier systems.

Such power amplifier systems can be implemented in various electronicdevices. Examples of the electronic devices can include, but are notlimited to, consumer electronic products, parts of the consumerelectronic products, electronic test equipment, etc. Examples of theelectronic devices can also include, but are not limited to, memorychips, memory modules, circuits of optical networks or othercommunication networks, and disk driver circuits. The consumerelectronic products can include, but are not limited to, a mobile phone,a telephone, a television, a computer monitor, a computer, a hand-heldcomputer, a personal digital assistant (PDA), a microwave, arefrigerator, an automobile, a stereo system, a cassette recorder orplayer, a DVD player, a CD player, a VCR, an MP3 player, a radio, acamcorder, a camera, a digital camera, a portable memory chip, a washer,a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, amulti functional peripheral device, a wrist watch, a clock, etc.Further, the electronic devices can include unfinished products.

CONCLUSION

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense, as opposed to anexclusive or exhaustive sense; that is to say, in the sense of“including, but not limited to.” The word “coupled”, as generally usedherein, refers to two or more elements that may be either directlyconnected, or connected by way of one or more intermediate elements.Likewise, the word “connected”, as generally used herein, refers to twoor more elements that may be either directly connected, or connected byway of one or more intermediate elements. Additionally, the words“herein,” “above,” “below,” and words of similar import, when used inthis application, shall refer to this application as a whole and not toany particular portions of this application. Where the context permits,words in the above Detailed Description using the singular or pluralnumber may also include the plural or singular number respectively. Theword “or” in reference to a list of two or more items, that word coversall of the following interpretations of the word: any of the items inthe list, all of the items in the list, and any combination of the itemsin the list.

Moreover, conditional language used herein, such as, among others,“can,” “could,” “might,” “can,” “e.g.,” “for example,” “such as” and thelike, unless specifically stated otherwise, or otherwise understoodwithin the context as used, is generally intended to convey that certainembodiments include, while other embodiments do not include, certainfeatures, elements and/or states. Thus, such conditional language is notgenerally intended to imply that features, elements and/or states are inany way required for one or more embodiments or that one or moreembodiments necessarily include logic for deciding, with or withoutauthor input or prompting, whether these features, elements and/orstates are included or are to be performed in any particular embodiment.

The above detailed description of embodiments of the invention is notintended to be exhaustive or to limit the invention to the precise formdisclosed above. While specific embodiments of, and examples for, theinvention are described above for illustrative purposes, variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize. For example, whileprocesses or blocks are presented in a given order, alternativeembodiments may perform routines having steps, or employ systems havingblocks, in a different order, and some processes or blocks may bedeleted, moved, added, subdivided, combined, and/or modified. Each ofthese processes or blocks may be implemented in a variety of differentways. Also, while processes or blocks are at times shown as beingperformed in series, these processes or blocks may instead be performedin parallel, or may be performed at different times.

The teachings of the invention provided herein can be applied to othersystems, not necessarily the system described above. The elements andacts of the various embodiments described above can be combined toprovide further embodiments.

While certain embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the disclosure. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the disclosure. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the disclosure.

1. (canceled)
 2. A power amplifier system comprising: an array oftransistor elements; a power amplifier including a bipolar poweramplifier transistor implemented by a plurality of transistor elementsof the array, the bipolar power amplifier transistor including a baseconfigured to receive a radio frequency input signal and a collectorconfigured to output an amplified radio frequency signal; and a biascircuit including a bipolar reference transistor implemented by one ormore transistor elements of the array, the bipolar reference transistorhaving a base electrically connected to the base of the bipolar poweramplifier transistor, the bias circuit further including a currentsource electrically connected to a collector of the bipolar referencetransistor and configured to generate a reference current.
 3. The poweramplifier system of claim 2 wherein the bias circuit further includes aselection circuit configured to select the one or more transistorelements from the array.
 4. The power amplifier system of claim 2wherein the bias circuit further includes an amplifier including aninput electrically connected to the collector of the reference bipolartransistor and an output configured to control a base voltage of thereference bipolar transistor.
 5. The power amplifier system of claim 4wherein the bias circuit further includes an isolation circuitelectrically connected between the output of the amplifier and the baseof the bipolar power amplifier transistor.
 6. The power amplifier systemof claim 4 wherein the amplifier is a transimpedance amplifier.
 7. Thepower amplifier system of claim 4 wherein the amplifier is configured tocontrol the base voltage such that a collector current of the bipolarreference transistor is substantially equal to the reference current. 8.The power amplifier system of claim 2 wherein the bias circuit furtherincludes a control circuit configured to control the reference currentto compensate for temperature variation.
 9. The power amplifier systemof claim 2 wherein each transistor element of the array has asubstantially identical geometry and is implemented in a common layout.10. A packaged module comprising: a package substrate; and asemiconductor die attached to the package substrate and including anarray of transistor elements in a common layout, the semiconductor diefurther including a bipolar power amplifier transistor implemented by aplurality of transistor elements of the array and configured to amplifya radio frequency input signal, a bipolar reference transistorimplemented by one or more transistor elements of the array and having abase electrically connected to a base of the bipolar power amplifiertransistor, and a current source electrically connected to a collectorof the bipolar reference transistor and configured to generate areference current.
 11. The packaged module of claim 10 wherein thesemiconductor die further includes an amplifier including an inputelectrically connected to the collector of the reference bipolartransistor and an output configured to control a base voltage of thereference bipolar transistor.
 12. The packaged module of claim 11wherein the semiconductor die further includes an isolation circuitelectrically connected between the output of the amplifier and the baseof the bipolar power amplifier transistor.
 13. The packaged module ofclaim 11 wherein the amplifier is a transimpedance amplifier.
 14. Thepackaged module of claim 11 wherein the amplifier is configured tocontrol the base voltage such that a collector current of the bipolarreference transistor is substantially equal to the reference current.15. The packaged module of claim 10 wherein the semiconductor diefurther includes a control circuit configured to control the referencecurrent to compensate for temperature variation.
 16. A mobile devicecomprising: a transceiver configured to generate a radio frequencysignal; a power amplifier system configured to amplify the radiofrequency signal to generate an amplified radio frequency signal, thepower amplifier system including an array of transistor elements, abipolar power amplifier transistor implemented by a plurality oftransistor elements of the array and having a collector configured tooutput the amplified radio frequency signal, a bipolar referencetransistor implemented by one or more transistor elements of the arrayand having a base electrically connected to a base of the bipolar poweramplifier transistor, and a current source electrically connected to acollector of the bipolar reference transistor and configured to generatea reference current; and an antenna configured to receive the amplifiedradio frequency signal from the power amplifier system.
 17. The mobiledevice of claim 16 wherein the power amplifier system further includesan amplifier including an input electrically connected to the collectorof the reference bipolar transistor and an output configured to controla base voltage of the reference bipolar transistor.
 18. The mobiledevice of claim 17 wherein the power amplifier system further includesan isolation circuit electrically connected between the output of theamplifier and the base of the bipolar power amplifier transistor. 19.The mobile device of claim 17 wherein the amplifier is a transimpedanceamplifier.
 20. The mobile device of claim 17 wherein the amplifier isconfigured to control the base voltage such that a collector current ofthe bipolar reference transistor is substantially equal to the referencecurrent.
 21. The mobile device of claim 16 wherein the power amplifiersystem further includes a control circuit configured to control thereference current to compensate for temperature variation.